1. Field of the Invention
The present invention relates to a stacked semiconductor package obtained by three-dimensionally stacking a plurality of semiconductor packages each having at least one semiconductor chip mounted thereon.
2. Related Background Art
Up to now, a semiconductor package to be used in an electronic equipment adopts a ball grid array (BGA) in which lands are formed in a grid pattern or a chip scale package (CSP) to thereby attain electronic equipments with a smaller size and a higher performance. Also, in recent years, as the electronic equipment grows more sophisticated, the electric circuits used therein become increasingly larger in size. Accordingly, in order to materialize an electric circuit with high density, a stacked semiconductor package in which semiconductor packages are three-dimensionally stacked is gradually used.
A system in package (SIP) structure and a package on package (POP) structure have been known as structures of a three-dimensionally stacked semiconductor package. Japanese Patent Application Laid-Open No. 2004-253667 discloses a stacked semiconductor package having the SIP structure. FIG. 16 shows a sectional view of a stacked semiconductor package having a typical SIP structure.
In FIG. 16, a printed wiring board 1001 has a stacked semiconductor package 1000 mounted thereon. The stacked semiconductor package 1000 has a two-layer structure composed of a first semiconductor package 1010 and a second semiconductor package 1020.
The first semiconductor package 1010 is formed of a first package substrate 1011, a first LSI 1012, and a solder ball group 1015. The first LSI 1012 is mounted on an upper surface of the first package substrate 1011 by a flip chip method, a wire bonding method, a CSP method, a BGA method, or the like. The solder ball group 1015 is provided on a lower surface of the first package substrate 1011 and is connected to the printed wiring board 1001.
The second semiconductor package 1020 is formed of a second package substrate 1021, a second LSI 1022, a third LSI 1023, and a solder ball group 1025. The second LSI 1022 and the third LSI 1023 are mounted on an upper surface of the second package substrate 1021 by a flip chip method, a wire bonding method, a CSP method, a BGA method, or the like. The solder ball group 1025 is provided on a lower surface of the second package substrate 1021.
The stacked semiconductor package 1000 is formed by joining the first semiconductor package 1010 and the second semiconductor package 1020 together with the solder ball group 1025. The stacked semiconductor package 1000 is mounted on the printed wiring board 1001 with the solder ball group 1015.
Usually, the LSI 1012 mounted on the first semiconductor package 1010 is an LSI which functions as a LOGIC circuit or an MPU circuit for providing functionality of a product. This is because, since the LOGIC circuit or the MPU circuit disposed on the first semiconductor package 1010 frequently transmits/receives a signal to/from a circuit on the printed wiring board, it is advantageous to dispose such the circuits adjacent to the printed wiring board 1001 in terms of the functionality of the product. On the other hand, the LSIs 1022 and 1023 mounted on the second semiconductor package 1020 are LSIs which function as a memory for data processing. The memories disposed in the second semiconductor package 1020 mostly transmit/receive a signal to/from the LOGIC circuit or the MPU circuit disposed in the first semiconductor package 1010. Therefore, it is advantageous to dispose such the memory adjacent to the LOGIC circuit or the MPU circuit rather than to the printed wiring board 1001 in terms of the functionality of the product.
Such the two-layer structure makes smaller the area on the printed wiring board 1001 occupied by components to thereby contribute to the higher density of an electronic equipment circuit. Further, the distance between the two semiconductor packages becomes smaller, which is also effective for higher speed communication between the LSIs.
Japanese Patent Application Laid-Open No. 2004-253667 discloses another method of manufacturing such a stacked semiconductor package. The disclosed method is described with reference to the stacked semiconductor package illustrated in FIG. 16. First, the second package substrate 1021 having the second LSI 1022 and the third LSI 1023 mounted thereon is flipped and fixed on a jig. Then, solder paste is printed on lands for solder connection which is formed in advance on the upper surface of the second package substrate 1021. Then, the first package substrate 1011 having the first LSI 1012 mounted thereon and having the solder ball group 1025 attached to the upper surface thereof is, in an flipped state, stacked on the second package substrate 1021 fixed on the jig. Here, the location of the solder ball group 1025 is adjusted so as to align with the solder paste printed on the lands for solder connection. After that, the stacked first package substrate 1011 and second package substrate 1021 are introduced into a reflow furnace together with the jig. By heating the inside of the furnace to a temperature higher than the melting points of the solder paste and of the solder ball group 1025 and then cooling them, the first package substrate 1011 and the second package substrate 1021 are joined together into the stacked semiconductor package.
In the stacked semiconductor package illustrated in FIG. 16, as described in the above, devices mounted in the second semiconductor package 1020 are usually LSIs which function as a memory for data processing. The structure as shown in FIG. 16 is very effective in transmitting/receiving a signal between LSIs 1022 and 1023 functioning as the memory and the LSI 1012 for functioning in a LOGIC circuit or an MPU circuit disposed in the first semiconductor package 1010. However, it is necessary that the LSIs 1022 and 1023 for functioning as the memory are required to be supplied not only with a signal from the LSI 1012 functioning in the LOGIC circuit or the MPU circuit but also with electric power and a ground (GND).
FIG. 17 is a sectional view illustrating a power supply path in the stacked semiconductor package 1000 illustrated in FIG. 16. In FIG. 17, the reference numeral 1050 denotes the power supply path, and the same reference numerals as those of FIG. 16 designate the same members to those shown in FIG. 16, respectively. As can be seen from FIG. 17, in the stacked semiconductor package 1000, the electric power and the GND are supplied to the LSIs 1022 and 1023 which function as the memory from the printed wiring board 1001 via the first semiconductor package 1010. More specifically, the path starts at the printed wiring board 1001 and goes through the solder ball group 1015, the first package substrate 1011, the solder ball group 1025, and the second package substrate 1021 to reach the LSIs 1022 and 1023. Therefore, the number of joints in the power supply path becomes large, and transmitting conditions in the path change significantly depending on the location. Therefore, fluctuation of its inductance in the power supply path becomes large, power bounce takes place, and it is difficult to obtain stable signal quality, which also prevents high speed signal communication.
When the second semiconductor package 1020 has a plurality of memory LSIs mounted therein with different power supply voltages, different power supply paths corresponding to the respective LSIs have to be provided. More specifically, both of the number of solder balls of the group 1015 for connecting the first package substrate 1011 and the printed wiring board 1001 and the number of solder balls of the group 1025 for connecting the layer package substrate 1011 and the second package substrate 1021 are required to be increased. Therefore, both the size of the first package substrate 1011 and the size of the second package substrate 1021 are increased.